3893 search results - page 606 / 779 » Execution Architectures and Compilation |
140
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SIGMETRICS
1996
ACM
15 years 9 months ago
1996
ACM
A large and increasing gap exists between processor and memory speeds in scalable cache-coherent multiprocessors. To cope with this situation, programmers and compiler writers mus...
192
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SIGMETRICS
1996
ACM
15 years 9 months ago
1996
ACM
This paper describes Embra, a simulator for the processors, caches, and memory systems of uniprocessors and cache-coherent multiprocessors. When running as part of the SimOS simul...
167
Voted
ISCA
1994
IEEE
15 years 9 months ago
1994
IEEE
We comparethe performance of software-supported shared memory on a general-purpose network to hardware-supported shared memory on a dedicated interconnect. Up to eight processors,...
184
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AOSD
2009
ACM
15 years 9 months ago
2009
ACM
Some security concerns are sensitive to flow of information in a program execution. The dataflow pointcut has been proposed by Masuhara and Kawauchi in order to easily implement s...
172
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CGO
2007
IEEE
15 years 9 months ago
2007
IEEE
In profiling, a tradeoff exists between information and overhead. For example, hardware-sampling profilers incur negligible overhead, but the information they collect is consequen...