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134
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MICRO
2005
IEEE
105views Hardware» more  MICRO 2005»
15 years 9 months ago
Incremental Commit Groups for Non-Atomic Trace Processing
We introduce techniques to support efficient non-atomic execution of very long traces on a new binary translation based, x86-64 compatible VLIW microprocessor. Incrementally comm...
Matt T. Yourst, Kanad Ghose
IPPS
2003
IEEE
15 years 9 months ago
Exploiting Java-ILP on a Simultaneous Multi-Trace Instruction Issue (SMTI) Processor
The available Instruction Level Parallelism in Java bytecode (Java-ILP) is not readily exploitable using traditional in-order or out-of-order issue mechanisms due to dependencies ...
R. Achutharaman, R. Govindarajan, G. Hariprakash, ...
185
Voted
IPPS
2003
IEEE
15 years 9 months ago
Applying Aspect-Orient Programming Concepts to a Component-Based Programming Model
Abstract— The execution environments For scientific applications have evolved significantly over the years. Vector and parallel architectures have provided significantly faste...
Thomas Eidson, Jack Dongarra, Victor Eijkhout
EUROPAR
1997
Springer
15 years 8 months ago
Modulo Scheduling with Cache Reuse Information
Instruction scheduling in general, and software pipelining in particular face the di cult task of scheduling operations in the presence of uncertain latencies. The largest contrib...
Chen Ding, Steve Carr, Philip H. Sweany
114
Voted
NIXDORF
1992
116views Hardware» more  NIXDORF 1992»
15 years 7 months ago
Programmable Active Memories: A Performance Assessment
We present some quantitative performance measurements for the computing power of Programmable Active Memories (PAM), as introduced by [2]. Based on Field Programmable Gate Array (...
Patrice Bertin, Didier Roncin, Jean Vuillemin