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IEEEPACT
2000
IEEE
15 years 2 months ago
Region Formation Analysis with Demand-Driven Inlining for Region-Based Optimization
Region-based compilation repartitions a program into more desirable compilation units for optimization and scheduling, particularly beneficial for ILP architectures. With region-...
Tom Way, Ben Breech, Lori L. Pollock
ISCA
1999
IEEE
105views Hardware» more  ISCA 1999»
15 years 2 months ago
The Program Decision Logic Approach to Predicated Execution
Modern compilers must expose sufficient amounts of Instruction-Level Parallelism (ILP) to achieve the promised performance increases of superscalar and VLIW processors. One of the...
David I. August, John W. Sias, Jean-Michel Puiatti...
CJ
2004
93views more  CJ 2004»
14 years 9 months ago
An Architecture for Kernel-Level Verification of Executables at Run Time
Digital signatures have been proposed by several researchers as a way of preventing execution of malicious code. In this paper we propose a general architecture for performing the...
Luigi Catuogno, Ivan Visconti
TWEB
2010
164views more  TWEB 2010»
14 years 8 months ago
A distributed service-oriented architecture for business process execution
The Business Process Execution Language (BPEL) standardizes the development of composite enterprise applications that make use of software components exposed as Web services. BPEL...
Guoli Li, Vinod Muthusamy, Hans-Arno Jacobsen
JUCS
2000
120views more  JUCS 2000»
14 years 9 months ago
Execution and Cache Performance of the Scheduled Dataflow Architecture
: This paper presents an evaluation of our Scheduled Dataflow (SDF) Processor. Recent focus in the field of new processor architectures is mainly on VLIW (e.g. IA-64), superscalar ...
Krishna M. Kavi, Joseph Arul, Roberto Giorgi