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ICASSP
2008
IEEE
15 years 4 months ago
Address assignment sensitive variable partitioning and scheduling for DSPS with multiple memory banks
Multiple memory banks design is employed in many high performance DSP processors. This architectural feature supports higher memory bandwidth by allowing multiple data memory acce...
Chun Jason Xue, Tiantian Liu, Zili Shao, Jingtong ...
WCRE
2002
IEEE
15 years 2 months ago
Analysis of Virtual Method Invocation for Binary Translation
The University of Queensland Binary Translator (UQBT ) is a static binary translation framework that allows for the translation of binary, executable programs, from one architectu...
Jens Tröger, Cristina Cifuentes
MICRO
1993
IEEE
131views Hardware» more  MICRO 1993»
15 years 2 months ago
Superblock formation using static program analysis
Compile-time code transformations which expose instruction-level parallelism (ILP) typically take into account the constraints imposed by all execution scenarios in the program. H...
Richard E. Hank, Scott A. Mahlke, Roger A. Bringma...
ISORC
2005
IEEE
15 years 3 months ago
On Real-Time Performance of Ahead-of-Time Compiled Java
One of the main challenges in getting acceptance for safe object-oriented languages in hard real-time systems is to combine automatic memory management with hard real-time constra...
Anders Nilsson, Sven Gestegard Robertz
FM
2006
Springer
134views Formal Methods» more  FM 2006»
15 years 1 months ago
Formal Verification of a C Compiler Front-End
This paper presents the formal verification of a compiler front-end that translates a subset of the C language into the Cminor intermediate language. The semantics of the source an...
Sandrine Blazy, Zaynah Dargaye, Xavier Leroy