3893 search results - page 89 / 779 » Execution Architectures and Compilation |
DAC
2011
ACM
13 years 9 months ago
2011
ACM
We present a high-level synthesis technique that takes as input two orthogonal descriptions: (a) a behavioral architectural contract between the implementation and the user, and (...
119
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FCCM
2011
IEEE
14 years 1 months ago
2011
IEEE
— This paper describes an architecture and FPGA synthesis toolchain for building specialized, energy-saving coprocessors called Irregular Code Energy Reducers (ICERs) for a wide ...
110
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ISSS
1995
IEEE
15 years 1 months ago
1995
IEEE
To construct complete systems on silicon, application speci c DSP accelerators are needed to speed up the execution of high throughput DSP algorithms. In this paper, a methodology...
101
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PC
2007
14 years 9 months ago
2007
We explore runtime mechanisms and policies for scheduling dynamic multi-grain parallelism on heterogeneous multi-core processors. Heterogeneous multi-core processors integrate con...
106
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ISHPC
2000
Springer
15 years 1 months ago
2000
Springer
This paper describes the implementation and evaluation of the OpenMP compiler designed for the Hitachi SR8000 Super Technical Server. The compiler performs parallelization for the ...