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CGO
2003
IEEE
15 years 3 months ago
Addressing Mode Selection
Many processor architectures provide a set of addressing modes in their address generation units. For example DSPs (digital signal processors) have powerful addressing modes for e...
Erik Eckstein, Bernhard Scholz
ML
2002
ACM
114views Machine Learning» more  ML 2002»
14 years 9 months ago
Building a Basic Block Instruction Scheduler with Reinforcement Learning and Rollouts
The execution order of a block of computer instructions on a pipelined machine can make a difference in running time by a factor of two or more. Compilers use heuristic schedulers...
Amy McGovern, J. Eliot B. Moss, Andrew G. Barto
TC
1998
14 years 9 months ago
Performance Evaluation and Cost Analysis of Cache Protocol Extensions for Shared-Memory Multiprocessors
—We evaluate three extensions to directory-based cache coherence protocols in shared-memory multiprocessors. These extensions are aimed at reducing the penalties associated with ...
Fredrik Dahlgren, Michel Dubois, Per Stenströ...
IEEEPACT
1998
IEEE
15 years 2 months ago
Dynamic Hammock Predication for Non-Predicated Instruction Set Architectures
Conventional speculative architectures use branch prediction to evaluate the most likely execution path during program execution. However, certain branches are difficult to predic...
Artur Klauser, Todd M. Austin, Dirk Grunwald, Brad...
LCPC
2005
Springer
15 years 3 months ago
Compiler Supports and Optimizations for PAC VLIW DSP Processors
Abstract. Compiler is substantially regarded as the most essential component in the software toolchain to promote a successful processor design. This paper describes our preliminar...
Yung-Chia Lin, Chung-Lin Tang, Chung-Ju Wu, Ming-Y...