Sciweavers

453 search results - page 73 / 91
» Execution and Cache Performance of the Scheduled Dataflow Ar...
Sort
View
JPDC
2010
106views more  JPDC 2010»
14 years 7 months ago
Feedback-directed page placement for ccNUMA via hardware-generated memory traces
Non-uniform memory architectures with cache coherence (ccNUMA) are becoming increasingly common, not just for large-scale high performance platforms but also in the context of mul...
Jaydeep Marathe, Vivek Thakkar, Frank Mueller
102
Voted
DAC
2003
ACM
15 years 10 months ago
A retargetable micro-architecture simulator
The capability of performing architectural exploration has become essential for embedded microprocessor design in System-On-Chip. While many retargetable instruction set (ISA) sim...
Wai Sum Mong, Jianwen Zhu
ICCAD
1994
IEEE
82views Hardware» more  ICCAD 1994»
15 years 1 months ago
Generating instruction sets and microarchitectures from applications
Abstract-- The design of application-specific instruction set processor (ASIP) system includes at least three interdependent tasks: microarchitecture design, instruction set design...
Ing-Jer Huang, Alvin M. Despain
76
Voted
RTSS
1996
IEEE
15 years 1 months ago
Integrated scheduling of multimedia and hard real-time tasks
An integrated platform which is capable of meeting the requirements of both traditional real-time control processing and multimedia processing has enormous potential for accommoda...
Hiroyuki Kaneko, John A. Stankovic, Subhabrata Sen...
EUROPAR
2001
Springer
15 years 1 months ago
Using a Swap Instruction to Coalesce Loads and Stores
A swap instruction, which exchanges a value in memory with a value of a register, is available on many architectures. The primary application of a swap instruction has been for pro...
Apan Qasem, David B. Whalley, Xin Yuan, Robert van...