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HPCN
1997
Springer
15 years 4 months ago
Performance Evaluation of HPCN Applications
The performance attained by parallel programs executed on multiprocessor systems is largely in uenced both by the characteristics of the code and by those of the system architectu...
Alessandro P. Merlo
MICRO
1992
IEEE
128views Hardware» more  MICRO 1992»
15 years 3 months ago
MISC: a Multiple Instruction Stream Computer
This paper describes a single chip Multiple Instruction Stream Computer (MISC) capable of extracting instruction level parallelism from a broad spectrum of programs. The MISC arch...
Gary S. Tyson, Matthew K. Farrens, Andrew R. Plesz...
BCB
2010
156views Bioinformatics» more  BCB 2010»
14 years 6 months ago
Accelerating HMMER on GPUs by implementing hybrid data and task parallelism
Many biologically motivated problems are expressed as dynamic programming recurrences and are difficult to parallelize due to the intrinsic data dependencies in their algorithms. ...
Narayan Ganesan, Roger D. Chamberlain, Jeremy Buhl...
COOPIS
2003
IEEE
15 years 5 months ago
DLS: A CORBA Service for Dynamic Loading of Code
Dynamic loading of code is needed when rarely used code should be loaded on demand or when the code to be loaded is not known in advance. In distributed systems it can also be used...
Rüdiger Kapitza, Franz J. Hauck
DAC
2005
ACM
15 years 1 months ago
Smart diagnostics for configurable processor verification
This paper describes a novel technique called Embedded Test-bench Control (ETC), extensively used in the verification of Tensilica’s latest configurable processor. Conventional ...
Sadik Ezer, Scott Johnson