Sciweavers

929 search results - page 125 / 186
» Execution architectures for program algebra
Sort
View
ISCA
1996
IEEE
99views Hardware» more  ISCA 1996»
15 years 4 months ago
Performance Comparison of ILP Machines with Cycle Time Evaluation
Many studies have investigated performance improvement through exploiting instruction-level parallelism (ILP) with a particular architecture. Unfortunately, these studies indicate...
Tetsuya Hara, Hideki Ando, Chikako Nakanishi, Masa...
DAC
2005
ACM
15 years 1 months ago
VLIW: a case study of parallelism verification
Parallelism in processor architecture and design imposes a verification challenge as the exponential growth in the number of execution combinations becomes unwieldy. In this paper...
Allon Adir, Yaron Arbetman, Bella Dubrov, Yossi Li...
KBSE
2010
IEEE
14 years 10 months ago
RESISTing reliability degradation through proactive reconfiguration
Situated software systems are an emerging class of systems that are predominantly pervasive, embedded, and mobile. They are marked with a high degree of unpredictability and dynam...
Deshan Cooray, Sam Malek, Roshanak Roshandel, Davi...
IPPS
2009
IEEE
15 years 6 months ago
Implementing and evaluating multithreaded triad census algorithms on the Cray XMT
Commonly represented as directed graphs, social networks depict relationships and behaviors among social entities such as people, groups, and organizations. Social network analysi...
George Chin Jr., Andrès Márquez, Sut...
LCTRTS
2007
Springer
15 years 6 months ago
Addressing instruction fetch bottlenecks by using an instruction register file
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...
Stephen Roderick Hines, Gary S. Tyson, David B. Wh...