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» Execution architectures for program algebra
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FPL
2010
Springer
267views Hardware» more  FPL 2010»
14 years 9 months ago
A Comparison of Hardware Acceleration Interfaces in a Customizable Soft Core Processor
Due to the continuously decreasing cost of FPGAs, they have become a valid implementation platform for SOCs. Typically, a soft core processor implementation is used to execute the ...
Gerald Hempel, Christian Hochberger, Andreas Koch
DSD
2011
IEEE
200views Hardware» more  DSD 2011»
13 years 11 months ago
Microthreading as a Novel Method for Close Coupling of Custom Hardware Accelerators to SVP Processors
Abstract—We present a new low-level interfacing scheme for connecting custom accelerators to processors that tolerates latencies that usually occur when accessing hardware accele...
Jaroslav Sykora, Leos Kafka, Martin Danek, Lukas K...
DAC
2008
ACM
16 years 25 days ago
Predictive runtime verification of multi-processor SoCs in SystemC
Concurrent interaction of multi-processor systems result in errors which are difficult to find. Traditional simulationbased verification techniques remove the concurrency informat...
Alper Sen, Vinit Ogale, Magdy S. Abadir
CASES
2006
ACM
15 years 3 months ago
Power efficient branch prediction through early identification of branch addresses
Ever increasing performance requirements have elevated deeply pipelined architectures to a standard even in the embedded processor domain, requiring the incorporation of dynamic b...
Chengmo Yang, Alex Orailoglu
JTRES
2010
ACM
15 years 20 hour ago
The embedded Java benchmark suite JemBench
Requirements to embedded systems increase steadily. In parallel, also the performance of the processors used in these systems is improved leading to multithreaded and/or multicore...
Martin Schoeberl, Thomas B. Preußer, Sascha ...