929 search results - page 159 / 186 » Execution architectures for program algebra |
95
Voted
SASP
2008
IEEE
15 years 6 months ago
2008
IEEE
—Accelerators are special purpose processors designed to speed up compute-intensive sections of applications. Two extreme endpoints in the spectrum of possible accelerators are F...
ASPLOS
2004
ACM
15 years 5 months ago
2004
ACM
We present a novel processor architecture designed specifically for use in low-power wireless sensor-network nodes. Our sensor network asynchronous processor (SNAP/LE) is based on...
HPCA
2005
IEEE
16 years 4 days ago
2005
IEEE
The use of large instruction windows coupled with aggressive out-oforder and prefetching capabilities has provided significant improvements in processor performance. In this paper...
112
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CGO
2005
IEEE
15 years 5 months ago
2005
IEEE
Software code caches are becoming ubiquitous, in dynamic optimizers, runtime tool platforms, dynamic translators, fast simulators and emulators, and dynamic compilers. Caching fre...
CODES
2005
IEEE
15 years 5 months ago
2005
IEEE
Even after carefully tuning the memory characteristics to the application properties and the processor speed, during the execution of real applications there are times when the pr...