929 search results - page 77 / 186 » Execution architectures for program algebra |
129
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MICRO
2010
IEEE
14 years 10 months ago
2010
IEEE
Since the non-cache parts of a core are less regular, compared to on-chip caches, tolerating manufacturing defects in the processing core is a more challenging problem. Due to the ...
116
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KDD
2005
ACM
16 years 3 months ago
2005
ACM
Computer architects utilize simulation tools to evaluate the merits of a new design feature. The time needed to adequately evaluate the tradeoffs associated with adding any new fe...
104
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ASPLOS
2006
ACM
15 years 9 months ago
2006
ACM
Growing on-chip wire delays are motivating architectural features that expose on-chip communication to the compiler. EDGE architectures are one example of communication-exposed mi...
132
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ASPLOS
1989
ACM
15 years 7 months ago
1989
ACM
A very long instruction word (VLIW) processorexploits parallelism by controlling multiple operations in a single instruction word. This paper describes the architecture and compil...
125
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JSA
2000
15 years 3 months ago
2000
Integrating processors and main memory is a promising approach to increase system performance. Such integration provides very high memory bandwidth that can be exploited efficientl...