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ISCA
2006
IEEE
125views Hardware» more  ISCA 2006»
15 years 9 months ago
Architectural Semantics for Practical Transactional Memory
Transactional Memory (TM) simplifies parallel programming by allowing for parallel execution of atomic tasks. Thus far, TM systems have focused on implementing transactional stat...
Austen McDonald, JaeWoong Chung, Brian D. Carlstro...
PDCAT
2007
Springer
15 years 9 months ago
A Distributed Virtual Machine for Parallel Graph Reduction
We present the architecture of nreduce, a distributed virtual machine which uses parallel graph reduction to run programs across a set of computers. It executes code written in a ...
Peter M. Kelly, Paul D. Coddington, Andrew L. Wend...
CODES
2005
IEEE
15 years 8 months ago
Dynamic phase analysis for cycle-close trace generation
For embedded system development, several companies provide cross-platform development tools to aid in debugging, prototyping and optimization of programs. These are full system em...
Cristiano Pereira, Jeremy Lau, Brad Calder, Rajesh...
HPCC
2007
Springer
15 years 9 months ago
File and Memory Security Analysis for Grid Systems
The grid security architecture today does not prevent certain unauthorized access to the files associated with a job executing on a remote machine. Programs and data are transferre...
Unnati Thakore, Lorie M. Liebrock
CGO
2007
IEEE
15 years 9 months ago
Exploiting Narrow Accelerators with Data-Centric Subgraph Mapping
The demand for high performance has driven acyclic computation accelerators into extensive use in modern embedded and desktop architectures. Accelerators that are ideal from a sof...
Amir Hormati, Nathan Clark, Scott A. Mahlke