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» Execution architectures for program algebra
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ICCD
2006
IEEE
157views Hardware» more  ICCD 2006»
16 years 6 days ago
Dynamic Co-Processor Architecture for Software Acceleration on CSoCs
By integrating one or more (hard or soft) CPU core on the chip, new generation platform FPGAs have become configurable systems on a chip (CSoC) that support a combined software an...
Abhishek Mitra, Zhi Guo, Anirban Banerjee, Walid A...
ICNS
2009
IEEE
15 years 10 months ago
Proactive Future Internet: Smart Semantic Middleware for Overlay Architecture
Some initiatives towards Future Internet, e.g., GENI, DARPA’s Active Networks, argue the need for programmability of the network components. Some other initiatives extend this w...
Vagan Y. Terziyan, Dmytro Zhovtobryukh, Artem Kata...
DSN
2008
IEEE
15 years 9 months ago
A fault-tolerant directory-based cache coherence protocol for CMP architectures
Current technology trends of increased scale of integration are pushing CMOS technology into the deepsubmicron domain, enabling the creation of chips with a significantly greater...
Ricardo Fernández Pascual, José M. G...
VL
2005
IEEE
137views Visual Languages» more  VL 2005»
15 years 8 months ago
CAM: A Mobile Paper-Based Information Services Architecture for Remote Rural Areas in the Developing World
During our work with microfinance groups in rural India, we found that paper plays a crucial role in many local information practices. However, paperbased record keeping can be in...
Tapan S. Parikh
ISCAS
2002
IEEE
154views Hardware» more  ISCAS 2002»
15 years 8 months ago
Architectural approaches to reduce leakage energy in caches
In this paper, we present two methods to reduce leakage energy by dynamically resizing the cache during program execution. The first method monitors the miss rate of the individua...
S. H. Tadas, C. Chakrabarti