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136
Voted
DATE
2009
IEEE
125views Hardware» more  DATE 2009»
15 years 12 months ago
HLS-l: High-level synthesis of high performance latch-based circuits
An inherent performance gap between custom designs and ASICs is one of the reasons why many designers still start their designs from register transfer level (RTL) description rath...
Seungwhun Paik, Insup Shin, Youngsoo Shin
162
Voted
DATE
2005
IEEE
91views Hardware» more  DATE 2005»
15 years 10 months ago
Reliability-Centric High-Level Synthesis
Importance of addressing soft errors in both safety critical applications and commercial consumer products is increasing, mainly due to ever shrinking geometries, higher-density c...
Suleyman Tosun, Nazanin Mansouri, Ercument Arvas, ...
ACMIDC
2010
15 years 9 months ago
Mobile collaboration: collaboratively reading and creating children's stories on mobile devices
This paper discusses design iterations of Mobile Stories – a mobile technology that empowers children to collaboratively read and create stories. We present the design and discu...
Jerry Alan Fails, Allison Druin, Mona Leigh Guha
ETS
2011
IEEE
224views Hardware» more  ETS 2011»
14 years 4 months ago
AVF Analysis Acceleration via Hierarchical Fault Pruning
—The notion of Architectural Vulnerability Factor (AVF) has been extensively used by designers to evaluate various aspects of design robustness. While AVF is a very accurate way ...
Michail Maniatakos, Chandra Tirumurti, Abhijit Jas...
144
Voted
ICSE
2008
IEEE-ACM
16 years 5 months ago
Creating a cognitive metric of programming task difficulty
Conducting controlled experiments about programming activities often requires the use of multiple tasks of similar difficulty. In previously reported work about a controlled exper...
Brian de Alwis, Gail C. Murphy, Shawn Minto