76 search results - page 3 / 16 » Experiences Developing an E-Whiteboard-Based Circuit Designe... |
ICRA
1994
IEEE
15 years 1 months ago
1994
IEEE
We describe a cost-effective method for developing parallel architectures which increase the performance of range and image sensors. A parametrised edge detector and its systolic ...
VLSID
2000
IEEE
15 years 1 months ago
2000
IEEE
Diagnosis algorithms targeting design errors in RTL circuit descriptions are presented in this paper. The algorithms presented exploit the hierarchy available in RTL designs to lo...
ISVLSI
2007
IEEE
15 years 3 months ago
2007
IEEE
In this work, we present a genetic algorithm based automated circuit synthesis framework for passive analog circuits. A procedure is developed for the simultaneous generation of b...
ISQED
2006
IEEE
15 years 3 months ago
2006
IEEE
Due to aggressive technology scaling, VLSI circuits are becoming increasingly susceptible to transient errors caused by single-event-upsets (SEUs). In this paper, we introduce two...
DAC
2005
ACM
14 years 11 months ago
2005
ACM
The need to reuse the performance macromodels of an analog circuit topology challenges existing regression based modeling techniques. A model of good reusability should have a num...