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» Experiences with the DEVStone benchmark
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90
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ICCD
2002
IEEE
152views Hardware» more  ICCD 2002»
15 years 9 months ago
Register Binding Based Power Management for High-level Synthesis of Control-Flow Intensive Behaviors
A circuit or circuit component that does not contain any spurious switching activity, i.e., activity that is not required by its specified functionality, is called perfectly power...
Lin Zhong, Jiong Luo, Yunsi Fei, Niraj K. Jha
98
Voted
ICCAD
2006
IEEE
126views Hardware» more  ICCAD 2006»
15 years 9 months ago
Exploring linear structures of critical path delay faults to reduce test efforts
It has been shown that the delay of a target path can be composed linearly of other path delays. If the later paths are robustly testable (with known delay values), the target pat...
Shun-Yen Lu, Pei-Ying Hsieh, Jing-Jia Liou
ICCAD
2002
IEEE
87views Hardware» more  ICCAD 2002»
15 years 9 months ago
A novel framework for multilevel routing considering routability and performance
We propose in this paper a novel framework for multilevel routing considering both routability and performance. The two-stage multilevel framework consists of coarsening followed ...
Shih-Ping Lin, Yao-Wen Chang
86
Voted
ICCAD
2002
IEEE
146views Hardware» more  ICCAD 2002»
15 years 9 months ago
Conflict driven learning in a quantified Boolean Satisfiability solver
Within the verification community, there has been a recent increase in interest in Quantified Boolean Formula evaluation (QBF) as many interesting sequential circuit verification ...
Lintao Zhang, Sharad Malik
97
Voted
FPGA
2010
ACM
243views FPGA» more  FPGA 2010»
15 years 9 months ago
Bit-level optimization for high-level synthesis and FPGA-based acceleration
d hardware design from behavior-level abstraction has drawn wide interest in FPGA-based acceleration and configurable computing research field. However, for many high-level progra...
Jiyu Zhang, Zhiru Zhang, Sheng Zhou, Mingxing Tan,...