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» Experiences with the DEVStone benchmark
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134
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ISQED
2006
IEEE
109views Hardware» more  ISQED 2006»
15 years 6 months ago
Dual-K Versus Dual-T Technique for Gate Leakage Reduction : A Comparative Perspective
As a result of aggressive technology scaling, gate leakage (gate oxide direct tunneling) has become a major component of total power dissipation. Use of dielectrics of higher perm...
Saraju P. Mohanty, Ramakrishna Velagapudi, Elias K...
92
Voted
MICRO
2006
IEEE
103views Hardware» more  MICRO 2006»
15 years 6 months ago
NoSQ: Store-Load Communication without a Store Queue
This paper presents NoSQ (short for No Store Queue), a microarchitecture that performs store-load communication without a store queue and without executing stores in the outof-ord...
Tingting Sha, Milo M. K. Martin, Amir Roth
105
Voted
SCAM
2006
IEEE
15 years 6 months ago
Constructing Accurate Application Call Graphs For Java To Model Library Callbacks
Call graphs are widely used to represent calling relationships among methods. However, there is not much interest in calling relationships among library methods in many software e...
Weilei Zhang, Barbara G. Ryder
88
Voted
ASPDAC
2006
ACM
105views Hardware» more  ASPDAC 2006»
15 years 6 months ago
Speed binning aware design methodology to improve profit under parameter variations
—Designing high-performance systems with high yield under parameter variations has raised serious design challenges in nanometer technologies. In this paper, we propose a profit-...
Animesh Datta, Swarup Bhunia, Jung Hwan Choi, Saib...
97
Voted
ISPD
2006
ACM
108views Hardware» more  ISPD 2006»
15 years 6 months ago
Statistical clock tree routing for robustness to process variations
Advances in VLSI technology make clock skew more susceptible to process variations. Notwithstanding efficient zero skew routing algorithms, clock skew still limits post-manufactu...
Uday Padmanabhan, Janet Meiling Wang, Jiang Hu