Sciweavers

1256 search results - page 165 / 252
» Experiences with the DEVStone benchmark
Sort
View
114
Voted
CCGRID
2005
IEEE
15 years 6 months ago
Empirical evaluation of shared parallel execution on independently scheduled clusters
Parallel machines are typically space shared, or time shared such that only one application executes on a group of nodes at any given time. It is generally assumed that executing ...
M. Ghanesh, S. Kumar, Jaspal Subhlok
CGO
2005
IEEE
15 years 6 months ago
Sentinel PRE: Hoisting beyond Exception Dependency with Dynamic Deoptimization
Many excepting instructions cannot be removed by existing Partial Redundancy Elimination (PRE) algorithms because the ordering constraints must be preserved between the excepting ...
Rei Odaira, Kei Hiraki
CODES
2005
IEEE
15 years 6 months ago
Satisfying real-time constraints with custom instructions
Instruction-set extensible processors allow an existing processor core to be extended with application-specific custom instructions. In this paper, we explore a novel application...
Pan Yu, Tulika Mitra
DATE
2005
IEEE
128views Hardware» more  DATE 2005»
15 years 6 months ago
Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits
Nanometer circuits are becoming increasingly susceptible to soft-errors due to alpha-particle and atmospheric neutron strikes as device scaling reduces node capacitances and suppl...
Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhij...
111
Voted
DFT
2005
IEEE
83views VLSI» more  DFT 2005»
15 years 6 months ago
An ILP Formulation for Yield-driven Architectural Synthesis
Data flow graph dominant designs, such as communication video and audio applications, are common in today’s IC industry. In these designs, the datapath resources (e.g., adders,...
Zhaojun Wo, Israel Koren, Maciej J. Ciesielski