Sciweavers

1256 search results - page 59 / 252
» Experiences with the DEVStone benchmark
Sort
View
ASPDAC
1999
ACM
60views Hardware» more  ASPDAC 1999»
15 years 4 months ago
Timing Optimization of Logic Network Using Gate Duplication
We present a timing optimization algorithm based on the concept of gate duplication on the technologydecomposed network. We first examine the relationship between gate duplication...
Chun-hong Chen, Chi-Ying Tsui
EURODAC
1994
IEEE
128views VHDL» more  EURODAC 1994»
15 years 4 months ago
A component selection algorithm for high-performance pipelines
The use of a realistic component library with multiple implementations of operators, results in cost ef cient designs; slow components can then be used on non-critical paths and t...
Smita Bakshi, Daniel D. Gajski
DAC
1994
ACM
15 years 4 months ago
Boolean Matching Using Generalized Reed-Muller Forms
-- In this paper we present a new method for Boolean matching of completely specified Boolean functions. The canonical Generalized Reed-Muller forms are used as a powerful analysis...
Chien-Chung Tsai, Malgorzata Marek-Sadowska
85
Voted
EUROPAR
2007
Springer
15 years 3 months ago
Optimizing Chip Multiprocessor Work Distribution Using Dynamic Compilation
How can sequential applications benefit from the ubiquitous next generation of chip multiprocessors (CMP)? Part of the answer may be a dynamic execution environment that automatica...
Jisheng Zhao, Matthew Horsnell, Ian Rogers, Andrew...
ICANN
2009
Springer
15 years 3 months ago
Classification Based on Combination of Kernel Density Estimators
Abstract. A new classification algorithm based on combination of kernel density estimators is introduced. The method combines the estimators with different bandwidths what can be i...
Mateusz Kobos, Jacek Mandziuk