123 search results - page 4 / 25 » Experimenting with buffer sizes in routers |
MICRO
2006
IEEE
15 years 3 months ago
2006
IEEE
The advent of deep sub-micron technology has recently highlighted the criticality of the on-chip interconnects. As diminishing feature sizes have led to increases in global wiring...
COMCOM
2010
14 years 9 months ago
2010
We study the interaction between the MIMD (Multiplicative Increase Multiplicative Decrease) congestion control and a bottleneck router with Drop Tail buffer. We consider the probl...
CN
2010
14 years 9 months ago
2010
Most existing criteria [3], [5], [8] for sizing router buffers rely on explicit formulation of the relationship between buffer size and characteristics of Internet traffic. However...
NOCS
2009
IEEE
15 years 4 months ago
2009
IEEE
Conventional packet-switched on-chip routers provide good resource sharing while minimizing latencies through various techniques. A virtual channel (VC) is allocated on a per-pack...
ASPDAC
2009
ACM
15 years 1 months ago
2009
ACM
Abstract-- The increasing wire delay constraints in deep submicron VLSI designs have led to the emergence of scalable and modular Network-on-Chip (NoC) architectures. As the power ...