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» Experimenting with buffer sizes in routers
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DAC
2002
ACM
15 years 10 months ago
Efficient code synthesis from extended dataflow graphs for multimedia applications
This paper presents efficient automatic code synthesis techniques from dataflow graphs for multimedia applications. Since multimedia applications require large size buffers contai...
Hyunok Oh, Soonhoi Ha
ICPP
2002
IEEE
15 years 2 months ago
Design and Evaluation of Scalable Switching Fabrics for High-Performance Routers
This work considers switching fabrics with distributed packet routing to achieve high scalability and low costs. The considered switching fabrics are based on a multistage structu...
Nian-Feng Tzeng, Ravi C. Batchu
VLSID
2002
IEEE
120views VLSI» more  VLSID 2002»
15 years 9 months ago
Floorplan Evaluation with Timing-Driven Global Wireplanning, Pin Assignment and Buffer/Wire Sizing
We describe a new algorithm for floorplan evaluation using timing-driven buffered routing according to a prescribed buffer site map. Specifically, we describe a provably good mult...
Christoph Albrecht, Andrew B. Kahng, Ion I. Mandoi...
CNSR
2010
IEEE
164views Communications» more  CNSR 2010»
15 years 25 days ago
Buffered Crossbar Fabrics Based on Networks on Chip
— Buffered crossbar (CICQ) switches have shown a high potential in scaling Internet routers capacity. However, they require expensive on-chip buffers whose cost grows quadratical...
Lotfi Mhamdi, Kees Goossens, Iria Varela Senin
MICRO
2003
IEEE
161views Hardware» more  MICRO 2003»
15 years 2 months ago
Design and Implementation of High-Performance Memory Systems for Future Packet Buffers
In this paper we address the design of a future high-speed router that supports line rates as high as OC-3072 (160 Gb/s), around one hundred ports and several service classes. Bui...
Jorge García-Vidal, Jesús Corbal, Ll...