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» Experimenting with buffer sizes in routers
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ISPASS
2009
IEEE
15 years 4 months ago
Experiment flows and microbenchmarks for reverse engineering of branch predictor structures
Insights into branch predictor organization and operation can be used in architecture-aware compiler optimizations to improve program performance. Unfortunately, such details are ...
Vladimir Uzelac, Aleksandar Milenkovic
GLOBECOM
2009
IEEE
15 years 4 months ago
Emulation of Optical PIFO Buffers
—With recent advances in optical technology, we are closer to building all-optical routers than ever before. A major problem in this area, however, is the lack of all-optical mem...
Houman Rastegarfar, Monia Ghobadi, Yashar Ganjali
CF
2008
ACM
14 years 11 months ago
Multi-terabit ip lookup using parallel bidirectional pipelines
To meet growing terabit link rates, highly parallel and scalable architectures are needed for IP lookup engines in next generation routers. This paper proposes an SRAM-based multi...
Weirong Jiang, Viktor K. Prasanna
110
Voted
TVLSI
2008
157views more  TVLSI 2008»
14 years 9 months ago
Scalable QoS-Aware Memory Controller for High-Bandwidth Packet Memory
This paper proposes a high-performance scalable quality-of-service (QoS)-aware memory controller for the packet memory where packet data are stored in network routers. A major chal...
Hyuk-Jun Lee, Eui-Young Chung
85
Voted
SAINT
2007
IEEE
15 years 3 months ago
SPRED: Active Queue Management Mechanism for Wide-Area Networks
AQM (Active Queue Management) mechanism is a congestion control mechanism at a router for controlling the number of packets in the router’s buffer by actively discarding an arri...
Hiroyuki Ohsaki, Hideyuki Yamamoto, Makoto Imase