A group testing-based BIST technique to identify faulty hard cores in FPGA devices is presented. The method provides for isolation of faults in embedded cores as demonstrated by ex...
Alireza Sarvi, Carthik A. Sharma, Ronald F. DeMara
A studentized range test using a two-stage and a one-stage sampling procedures, respectively, is proposed for testing the hypothesis that the average deviation of the normal means...
Abstract. The paper outlines an experiment conducted in two different academic environments, in which FIT tests were used as a functional requirements specification. Common challen...
We present a sufficient linear-time schedulability test for preemptable, asynchronous, periodic task systems with arbitrary relative deadlines, scheduled on a uniprocessor by an ...
1 This paper presents a test input data compression technique, which can be used to reduce input test data volume, test time, and the number of required tester channels. The techni...