504 search results - page 4 / 101 » Explaining Verification Conditions |
TARK
2007
Springer
15 years 3 months ago
2007
Springer
We give derivations of two formal models of Gricean Quantity1 implicature and strong exhaustivity (Van Rooij and Schulz, 2004; Schulz and Van Rooij, 2006), in bidirectional optima...
CSCW
2002
ACM
14 years 9 months ago
2002
ACM
We present an experiment examining effects of gaze on speech during three-person conversations. Understanding such effects is crucial for the design of teleconferencing systems an...
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DAGSTUHL
2006
14 years 11 months ago
2006
The methodology of aspect-oriented software engineering has been proposed to factor out concerns that are orthogonal to the core functionality of a system. In particular, this is a...
SAC
2010
ACM
14 years 7 months ago
2010
ACM
Verification conditions (VCs) are logical formulae whose validity implies the correctness of a program with respect to a specification. The technique of checking software properti...
ACSC
2004
IEEE
15 years 1 months ago
2004
IEEE
This paper introduces a repeatable and constructive approach to the analysis of loop progress and termination conditions in imperative programs. It is applicable to all loops for ...