375 search results - page 16 / 75 » Explicit gate delay model for timing evaluation |
127
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TVLSI
2008
15 years 1 months ago
2008
Abstract--Technology scaling in the nanometer era has increased the transistor's susceptibility to process variations. The effects of such variations are having a huge impact ...
103
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DATE
2007
IEEE
15 years 8 months ago
2007
IEEE
— We present a waveform based variational static timing analysis methodology. It is a timing paradigm that lies midway between convention static delay approximations and full dyn...
109
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VLSID
2005
IEEE
16 years 2 months ago
2005
IEEE
This paper employs general multivariate normal distribution to develop a new efficient statistical timing analysis methodology. The paper presents the theoretical framework of the...
125
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TCAD
2008
15 years 1 months ago
2008
Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the mos...
110
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DATE
2003
IEEE
15 years 7 months ago
2003
IEEE
The growing impact of within-die process variation has created the need for statistical timing analysis, where gate delays are modeled as random variables. Statistical timing anal...