375 search results - page 22 / 75 » Explicit gate delay model for timing evaluation |
87
Voted
ASYNC
2002
IEEE
15 years 6 months ago
2002
IEEE
Advanced clock-delayed1 and self-resetting domino circuits are becoming increasingly important design styles in aggressive synchronous as well as asynchronous design. Their design...
106
Voted
ICPADS
2007
IEEE
15 years 8 months ago
2007
IEEE
In this paper, we propose a real time scheduling policy over 802.11 DCF protocol called Deadline Monotonic (DM). We evaluate the performance of this policy for a simple scenario w...
114
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ICCAD
1996
IEEE
15 years 6 months ago
1996
IEEE
Elmore delay has been widely used as an analytical estimate of interconnect delays in the performance-driven synthesis and layout of VLSI routing topologies. However,for typical R...
102
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WSC
2004
15 years 3 months ago
2004
Metering flights at key points such as sector crossings is an important operational procedure in mitigating National Airspace System (NAS) traffic congestion due to high demand or...
114
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NETWORKING
2007
15 years 3 months ago
2007
We evaluate the performance of a class of two-hop relay protocols for mobile ad hoc networks. The interest is on the multicopy two-hop relay (MTR) protocol, where the source may ge...