375 search results - page 23 / 75 » Explicit gate delay model for timing evaluation |
113
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TCAD
2008
15 years 1 months ago
2008
Physical synthesis tools are responsible for achieving timing closure. Starting with 130nm designs, multiple cycles are required to cross the chip, making latch placement critical...
99
Voted
ANSS
2001
IEEE
15 years 5 months ago
2001
IEEE
We present the definition of diverse models of physical systems using the Cell-DEVS paradigm. Cell-DEVS is an extension of the DEVS formalism that allows the definition of cellula...
111
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ICCD
2004
IEEE
15 years 10 months ago
2004
IEEE
A cache access time model, PRACTICS (PRedictor of Access and Cycle TIme for Cache Stack), has been developed to optimize the memory array architecture for the minimum access and c...
94
Voted
DAC
2007
ACM
16 years 2 months ago
2007
ACM
It is known that ramp-based models are not sufficient for accurate timing modeling. In this paper, we develop a technique that accurately models the waveforms, and also allows a f...
116
Voted
ISQED
2007
IEEE
15 years 8 months ago
2007
IEEE
In nanometer regime, the effects of variations are having an increasing impact on the delay and power characteristics of devices as well as the yield of the circuit. Statistical t...