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» Explicit gate delay model for timing evaluation
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TVLSI
2002
144views more  TVLSI 2002»
15 years 1 months ago
On-chip inductance cons and pros
Abstract--This paper provides a high level survey of the increasing effects of on-chip inductance. These effects are classified into desirable and nondesirable effects. Among the u...
Yehea I. Ismail
DATE
2009
IEEE
114views Hardware» more  DATE 2009»
15 years 8 months ago
Hardware aging-based software metering
Abstract—Reliable and verifiable hardware, software and content usage metering (HSCM) are of primary importance for wide segments of e-commerce including intellectual property a...
Foad Dabiri, Miodrag Potkonjak
134
Voted
TKDE
2011
150views more  TKDE 2011»
14 years 8 months ago
Estimating and Enhancing Real-Time Data Service Delays: Control-Theoretic Approaches
—It is essential to process real-time data service requests such as stock quotes and trade transactions in a timely manner using fresh data, which represent the current real worl...
Kyoung-Don Kang, Yan Zhou, Jisu Oh
ICCAD
2006
IEEE
146views Hardware» more  ICCAD 2006»
15 years 10 months ago
An analytical model for negative bias temperature instability
— Negative Bias Temperature Instability (NBTI) in PMOS transistors has become a significant reliability concern in present day digital circuit design. With continued scaling, th...
Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatneka...
98
Voted
INFOCOM
2005
IEEE
15 years 7 months ago
Analysis of alternating-priority queueing models with (cross) correlated switchover times
This paper analyzes a single server queueing system in which service is alternated between two queues and the server requires a (finite) switchover time to switch from one queue ...
Robin Groenevelt, Eitan Altman