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» Explicit gate delay model for timing evaluation
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EUROGP
2007
Springer
102views Optimization» more  EUROGP 2007»
15 years 8 months ago
Real-Time, Non-intrusive Evaluation of VoIP
Abstract. Speech quality, as perceived by the users of Voice over Internet Protocol (VoIP) telephony, is critically important to the uptake of this service. VoIP quality can be deg...
Adil Raja, R. Muhammad Atif Azad, Colin Flanagan, ...
HPCA
2009
IEEE
16 years 2 months ago
Accurate microarchitecture-level fault modeling for studying hardware faults
Decreasing hardware reliability is expected to impede the exploitation of increasing integration projected by Moore's Law. There is much ongoing research on efficient fault t...
Man-Lap Li, Pradeep Ramachandran, Ulya R. Karpuzcu...
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IWCMC
2006
ACM
15 years 7 months ago
Queuing network models for delay analysis of multihop wireless ad hoc networks
— In this paper we focus on characterizing the average end-to-end delay and maximum achievable per-node throughput in random access multihop wireless ad hoc networks with station...
Nabhendra Bisnik, Alhussein A. Abouzeid
ICCAD
2003
IEEE
175views Hardware» more  ICCAD 2003»
15 years 10 months ago
Path Delay Estimation using Power Supply Transient Signals: A Comparative Study using Fourier and Wavelet Analysis
Transient Signal Analysis (TSA) is a parametric device testing technique based on the analysis of dynamic (transient) current (iDDT) drawn by the core logic from the power supply ...
Abhishek Singh, Jitin Tharian, Jim Plusquellic
VLSID
2005
IEEE
102views VLSI» more  VLSID 2005»
16 years 2 months ago
Integrated On-Chip Storage Evaluation in ASIP Synthesis
An Application Specific Instruction Set Processor (ASIP) exploits special characteristics of the given application(s) to meet the desired performance, cost and power requirements....
Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar