375 search results - page 5 / 75 » Explicit gate delay model for timing evaluation |
ISMVL
2007
IEEE
15 years 8 months ago
2007
IEEE
The clock rate of modern chips is still increasing and at the same time the gate size decreases. As a result, already slight variations during the production process may cause a f...
85
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DAC
2002
ACM
16 years 2 months ago
2002
ACM
In this paper, a new type of Petri net called Hierarchical Colored Hardware Petri net, to model real-delay switching activity for power estimation is proposed. The logic circuit i...
101
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ICCAD
2005
IEEE
15 years 10 months ago
2005
IEEE
— As technology scales into the sub-90nm domain, manufacturing variations become an increasingly significant portion of circuit delay. As a result, delays must be modeled as sta...
117
Voted
GLVLSI
2003
IEEE
15 years 7 months ago
2003
IEEE
—Interconnect inductance introduces a shielding effect which decreases the effective capacitance seen by the driver of a circuit, reducing the gate delay. A model of the effectiv...
ICCD
2001
IEEE
15 years 10 months ago
2001
IEEE
‡ Physical and generic models that analytically couple the array architecture of CMOS SRAMs with the wire lengths and fan-outs along critical paths to decode and sense data are r...