The goal of this work was to test whether the performance of a regular pairwise classifier can be improved when additional information about the hierarchical class structure is ad...
Instances of the Boolean satisfiability problem (SAT) arise in many areas of circuit design and verification. These instances are typically constructed from some human-designed ar...
Paul T. Darga, Mark H. Liffiton, Karem A. Sakallah...
We propose a new bandwidth allocation scheme for VBR video tra c in ATM networks. The scheme is tailored to MPEG-coded video sources that require stringent and deterministic quali...
Previous studies have demonstrated that encoding a Bayesian network into a SAT formula and then performing weighted model counting using a backtracking search algorithm can be an ...
Simulation is an important means of evaluating new microarchitectures. Current trends toward chip multiprocessors (CMPs) try the ability of designers to develop efficient simulato...
David A. Penry, Daniel Fay, David Hodgdon, Ryan We...