87 search results - page 7 / 18 » Exploiting Instruction Redundancy for Transient Fault Tolera... |
DSN
2005
IEEE
15 years 5 months ago
2005
IEEE
Designing a distributed fault tolerance algorithm requires careful analysis of both fault models and diagnosis strategies. A system will fail if there are too many active faults, ...
114
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ICCD
2003
IEEE
15 years 8 months ago
2003
IEEE
Continued advancements in fabrication technology and reductions in feature size create challenges in maintaining both manufacturing yield rates and long-term reliability of device...
112
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DSD
2010
IEEE
14 years 9 months ago
2010
IEEE
Abstract--Recent technology trends have made radiationinduced soft errors a growing threat to the reliability of microprocessors, a problem previously only known to the aerospace i...
RTS
2006
14 years 11 months ago
2006
Abstract. The Time-Triggered Architecture, as architecture for safety-critical realtime applications, incorporates fault-tolerance mechanisms to ensure correct system operation des...
89
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DSN
2002
IEEE
15 years 4 months ago
2002
IEEE
The architecture and implementation of the LEON-FT processor is presented. LEON-FT is a fault-tolerant 32-bit processor based on the SPARC V8 instruction set. The processors toler...