Wires shrink less efficiently than transistors. Smaller dimensions increase relative delay and the probability of crosstalk. Solutions to this problem include adding additional lat...
As the thermal wall becomes the dominant factor limiting VLSI circuit performance, and the interconnect wires become the primary power consumer, power efficiency of onchip data th...
Renshen Wang, Evangeline F. Y. Young, Ronald L. Gr...
We analyze the technique for reducing the complexity of entropy coding consisting in the a priori grouping of the source alphabet symbols, and in dividing the coding process in tw...
To achieve minimum signal propagation delay, the nonuniform wire width routing architecture has been widely used in modern VLSI design. The non-uniform routing architecture exploi...
Abstract. In this paper we analyse a serial (ripple carry) and a parallel (Kogge-Stone) adder when operating in subthreshold at 100nm and 70nm. These are targeted for ultra low pow...