10 search results - page 2 / 2 » Exploiting On-Chip Memory Bandwidth in the VIRAM Compiler |
112
Voted
ICASSP
2008
IEEE
15 years 7 months ago
2008
IEEE
Multiple memory banks design is employed in many high performance DSP processors. This architectural feature supports higher memory bandwidth by allowing multiple data memory acce...
125
Voted
PPOPP
2009
ACM
16 years 1 months ago
2009
ACM
On multiprocessors with explicitly managed memory hierarchies (EMM), software has the responsibility of moving data in and out of fast local memories. This task can be complex and...
133
Voted
HPCA
1998
IEEE
15 years 5 months ago
1998
IEEE
The performance of a concurrent multithreaded architectural model, called superthreading 15 , is studied in this paper. It tries to integrate optimizing compilation techniques and...
120
Voted
PDPTA
2000
15 years 2 months ago
2000
Exploiting compile time knowledge to improve memory bandwidth can produce noticeable improvements at run-time [13, 1]. Allocating the data structure [13] to separate memories when...
103
Voted
ASPLOS
2010
ACM
15 years 4 months ago
2010
ACM
This paper proposes an efficient hardware/software system that significantly enhances software security through diversified replication on multi-cores. Recent studies show that a ...