94 search results - page 11 / 19 » Exploiting Speculative Thread-Level Parallelism on a SMT Pro... |
MICRO
1998
IEEE
15 years 1 months ago
1998
IEEE
The Multiscalar architecture advocates a distributed processor organization and task-level speculation to exploit high degrees of instruction level parallelism (ILP) in sequential...
LCPC
1999
Springer
15 years 1 months ago
1999
Springer
The traditional target machine of a parallelizing compiler can execute code sections either serially or in parallel. In contrast, targeting the generated code to a speculative para...
90
Voted
DATE
2007
IEEE
15 years 3 months ago
2007
IEEE
We are concerned with the software implementation of baseband processing for the physical layer of radio standards (“Software Defined Radio - SDR”). Given the constraints for ...
IPPS
2009
IEEE
15 years 4 months ago
2009
IEEE
DTA (Decoupled Threaded Architecture) is designed to exploit fine/medium grained Thread Level Parallelism (TLP) by using a distributed hardware scheduling unit and relying on exi...
MICRO
1997
IEEE
15 years 1 months ago
1997
IEEE
Compiler optimizations are often driven by specific assumptions about the underlying architecture and implementation of the target machine. For example, when targeting shared-mem...