94 search results - page 15 / 19 » Exploiting Speculative Thread-Level Parallelism on a SMT Pro... |
109
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IPPS
2010
IEEE
14 years 9 months ago
2010
IEEE
Abstract--The lag of parallel programming models and languages behind the advance of heterogeneous many-core processors has left a gap between the computational capability of moder...
APCSAC
2005
IEEE
15 years 5 months ago
2005
IEEE
In order to enhance the performance of a computer, most modern processors use superscalar architecture and raise the clock frequency. Superscalar architecture can execute more than...
115
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PPOPP
2003
ACM
15 years 4 months ago
2003
ACM
Speculative multithreading (SpMT) architecture can exploit thread-level parallelism that cannot be identified statically. Speedup can be obtained by speculatively executing threa...
105
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ISCA
2002
IEEE
14 years 11 months ago
2002
IEEE
Traditional vector architectures have shown to be very effective for regular codes where the compiler can detect data-level parallelism. However, this SIMD parallelism is also pre...
TPDS
2010
14 years 10 months ago
2010
—Thread-level parallelism (TLP) has been extensively studied in order to overcome the limitations of exploiting instruction-level parallelism (ILP) on high-performance superscala...