94 search results - page 7 / 19 » Exploiting Speculative Thread-Level Parallelism on a SMT Pro... |
ASPLOS
2010
ACM
15 years 4 months ago
2010
ACM
With the right techniques, multicore architectures may be able to continue the exponential performance trend that elevated the performance of applications of all types for decades...
155
Voted
GECCO
2009
Springer
14 years 7 months ago
2009
Springer
Simultaneous Multithreading (SMT) is a technology aimed at improving the throughput of the processor core by applying Instruction Level Parallelism (ILP) and Thread Level Parallel...
81
Voted
CODES
2006
IEEE
15 years 3 months ago
2006
IEEE
Embedded processors have been increasingly exploiting hardware parallelism. Vector units, multiple processors or cores, hyper-threading, special-purpose accelerators such as DSPs ...
IPPS
2006
IEEE
15 years 3 months ago
2006
IEEE
With the advent of chip-multiprocessors (CMPs), Thread-Level Speculation (TLS) remains a promising technique for exploiting this highly multithreaded hardware to improve the perfo...
ISCA
2000
IEEE
15 years 1 months ago
2000
IEEE
While architects understandhow to build cost-effective parallel machines across a wide spectrum of machine sizes (ranging from within a single chip to large-scale servers), the re...