94 search results - page 8 / 19 » Exploiting Speculative Thread-Level Parallelism on a SMT Pro... |
CSE
2008
IEEE
14 years 11 months ago
2008
IEEE
Parallel computing is widely used for large scale threedimensional simulation of seismic wave propagation. One particularity of most of these simulations is to consider a finite c...
ICCD
2006
IEEE
15 years 6 months ago
2006
IEEE
—This paper introduces the microarchitecture and logical implementation of SMT (Simultaneous Multithreading) improvement of Godson-2 processor which is a 64-bit, four-issue, out-...
SBACPAD
2007
IEEE
15 years 3 months ago
2007
IEEE
One way to exploit Thread Level Parallelism (TLP) is to use architectures that implement novel multithreaded execution models, like Scheduled DataFlow (SDF). This latter model pro...
ICS
1999
Tsinghua U.
15 years 1 months ago
1999
Tsinghua U.
In this paper we present a processor microarchitecture that can simultaneously execute multiple threads and has a clustered design for scalability purposes. A main feature of the ...
ICS
2007
Tsinghua U.
15 years 3 months ago
2007
Tsinghua U.
The register file is one of the most critical datapath components limiting the number of threads that can be supported on a Simultaneous Multithreading (SMT) processor. To allow t...