Sciweavers

40 search results - page 1 / 8
» Exploiting Value Locality in Physical Register Files
Sort
View
57
Voted
MICRO
2003
IEEE
121views Hardware» more  MICRO 2003»
15 years 2 months ago
Exploiting Value Locality in Physical Register Files
The physical register file is an important component of a dynamically-scheduled processor. Increasing the amount of parallelism places increasing demands on the physical register...
Saisanthosh Balakrishnan, Gurindar S. Sohi
90
Voted
ACSC
2004
IEEE
15 years 1 months ago
Reducing Register Pressure Through LAER Algorithm
When modern processors keep increasing the instruction window size and the issue width to exploit more instruction-level parallelism (ILP), the demand of larger physical register ...
Gao Song
DATE
2009
IEEE
105views Hardware» more  DATE 2009»
15 years 4 months ago
Exploiting narrow-width values for thermal-aware register file designs
—Localized heating-up creates thermal hotspots across the chip, with the integer register file ranked as the hottest unit in high-performance microprocessors. In this paper, we ...
Shuai Wang, Jie Hu, Sotirios G. Ziavras, Sung Woo ...
ICCD
2004
IEEE
101views Hardware» more  ICCD 2004»
15 years 6 months ago
Increasing Processor Performance Through Early Register Release
Modern superscalar microprocessors need sizable register files to support large number of in-flight instructions for exploiting ILP. An alternative to building large register file...
Oguz Ergin, Deniz Balkan, Dmitry V. Ponomarev, Kan...
ISLPED
2006
ACM
100views Hardware» more  ISLPED 2006»
15 years 3 months ago
Selective writeback: exploiting transient values for energy-efficiency and performance
Today’s superscalar microprocessors use large, heavily-ported physical register files (RFs) to increase the instruction throughput. The high complexity and power dissipation of ...
Deniz Balkan, Joseph J. Sharkey, Dmitry Ponomarev,...