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» Exploiting and Protecting Dynamic Code Generation
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83
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CODES
2004
IEEE
15 years 2 months ago
Automatic synthesis of system on chip multiprocessor architectures for process networks
In this paper, we present an approach for automatic synthesis of System on Chip (SoC) multiprocessor architectures for applications expressed as process networks. Our approach is ...
Basant Kumar Dwivedi, Anshul Kumar, M. Balakrishna...
142
Voted
CF
2011
ACM
13 years 10 months ago
SIFT: a low-overhead dynamic information flow tracking architecture for SMT processors
Dynamic Information Flow Tracking (DIFT) is a powerful technique that can protect unmodified binaries from a broad range of vulnerabilities such as buffer overflow and code inj...
Meltem Ozsoy, Dmitry Ponomarev, Nael B. Abu-Ghazal...
94
Voted
SIGMETRICS
2011
ACM
178views Hardware» more  SIGMETRICS 2011»
14 years 1 months ago
Soft error benchmarking of L2 caches with PARMA
The amount of charge stored in an SRAM cell shrinks rapidly with each technology generation thus increasingly exposing caches to soft errors. Benchmarking the FIT rate of caches d...
Jinho Suh, Mehrtash Manoochehri, Murali Annavaram,...
103
Voted
ISCA
1999
IEEE
187views Hardware» more  ISCA 1999»
15 years 2 months ago
Area Efficient Architectures for Information Integrity in Cache Memories
Information integrity in cache memories is a fundamental requirement for dependable computing. Conventional architectures for enhancing cache reliability using check codes make it...
Seongwoo Kim, Arun K. Somani
89
Voted
SAC
2006
ACM
15 years 4 months ago
Noxes: a client-side solution for mitigating cross-site scripting attacks
Web applications are becoming the dominant way to provide access to on-line services. At the same time, web application vulnerabilities are being discovered and disclosed at an al...
Engin Kirda, Christopher Krügel, Giovanni Vig...