383 search results - page 20 / 77 » Exploiting nonstationarity for performance prediction |
99
Voted
SAC
2006
ACM
15 years 3 months ago
2006
ACM
Modern embedded processors access the Branch Target Buffer (BTB) every cycle to speculate branch target addresses. Such accesses, quite often, are unnecessary as there is no branc...
JILP
2000
14 years 9 months ago
2000
We identify that a set of multimedia applications exhibit highly regular read-after-read (RAR) and read-after-write (RAW) memory dependence streams. We exploit this regularity to ...
HPCA
2003
IEEE
15 years 10 months ago
2003
IEEE
To continue to improve processor performance, microarchitects seek to increase the effective instruction level parallelism (ILP) that can be exploited in applications. A fundament...
GLOBECOM
2009
IEEE
15 years 4 months ago
2009
IEEE
—Scheduling techniques are often deployed at the network edge to maximize the quality of the video communication while satisfying a given constraint on the maximum high priority ...
SBACPAD
2007
IEEE
15 years 4 months ago
2007
IEEE
The necessity of devising novel thread-level speculation (TLS) techniques has become extremely important with the growing acceptance of multi-core architectures by the industry. H...