42 search results - page 6 / 9 » Exploiting temporal locality in drowsy cache policies |
103
Voted
TC
1998
14 years 11 months ago
1998
—High instruction cache hit rates are key to high performance. One known technique to improve the hit rate of caches is to minimize cache interference by improving the layout of ...
113
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LCTRTS
2005
Springer
15 years 5 months ago
2005
Springer
Effective use of the memory hierarchy is critical for achieving high performance on embedded systems. We focus on the class of streaming applications, which is increasingly preval...
ICPP
1996
IEEE
15 years 3 months ago
1996
IEEE
Tiling exploits temporal reuse carried by an outer loop of a loop nest to enhance cache locality. Loop skewing is typically required to make tiling legal. This restricts parallelis...
100
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HPDC
1999
IEEE
15 years 3 months ago
1999
IEEE
In this paper, we present the design and implementation of Dodo, an e cient user-level system for harvesting idle memory in o -the-shelf clusters of workstations. Dodo enables dat...
158
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HPCA
2004
IEEE
15 years 12 months ago
2004
IEEE
Recent research suggests that there are large variations in a cache's spatial usage, both within and across programs. Unfortunately, conventional caches typically employ fixe...