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DATE
2005
IEEE
107views Hardware» more  DATE 2005»
15 years 10 months ago
Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique
Complex applications implemented as Systems on Chip (SoCs) demand extensive use of system level modeling and validation. Their implementation gathers a large number of complex IP ...
César A. M. Marcon, Ney Laert Vilar Calazan...
DATE
2005
IEEE
108views Hardware» more  DATE 2005»
15 years 10 months ago
A Technology-Aware and Energy-Oriented Topology Exploration for On-Chip Networks
As packet-switching interconnection networks replace buses and dedicated wires to become the standard on-chip interconnection fabric, reducing their power consumption has been ide...
Hangsheng Wang, Li-Shiuan Peh, Sharad Malik
DATE
2005
IEEE
134views Hardware» more  DATE 2005»
15 years 10 months ago
Assertion-Based Design Exploration of DVS in Network Processor Architectures
With the scaling of technology and higher requirements on performance and functionality, power dissipation is becoming one of the major design considerations in the development of...
Jia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang 000...
DSN
2005
IEEE
15 years 10 months ago
Small Parity-Check Erasure Codes - Exploration and Observations
James S. Plank, Adam L. Buchsbaum, Rebecca L. Coll...