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ICCD
1999
IEEE
122views Hardware» more  ICCD 1999»
15 years 2 months ago
Design and Evaluation of a Selective Compressed Memory System
This research explores any potential for an on-chip cache compression which can reduce not only cache miss ratio but also miss penalty, if main memory is also managed in compresse...
Jang-Soo Lee, Won-Kee Hong, Shin-Dug Kim
EUC
2006
Springer
15 years 1 months ago
Co-optimization of Performance and Power in a Superscalar Processor Design
Abstract. As process technology scales down, power wall starts to hinder improvements in processor performance. Performance optimization has to proceed under a power constraint. Th...
Yongxin Zhu, Weng-Fai Wong, Stefan Andrei
ASPDAC
2005
ACM
90views Hardware» more  ASPDAC 2005»
14 years 12 months ago
An integrated performance and power model for superscalar processor designs
— On current superscalar processors, performance and power issues cannot be decoupled for designers. Extensive simulations are usually required to meet both power and performance...
Yongxin Zhu, Weng-Fai Wong, Stefan Andrei
EHCI
2001
14 years 11 months ago
Modelling and Using Sensed Context Information in the Design of Interactive Applications
We present a way of analyzing sensed context information formulated to help in the generation, documentation and assessment of the designs of context-aware applications. Starting w...
Philip D. Gray, Daniel Salber
IJNSEC
2008
106views more  IJNSEC 2008»
14 years 10 months ago
Parallel Hardware Architectures for the Cryptographic Tate Pairing
Identity-based cryptography uses pairing functions,which are sophisticated bilinear maps defined on elliptic curves.Computing pairings efficiently in software is presently a relev...
Guido Marco Bertoni, Luca Breveglieri, Pasqualina ...