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» Exploring Design Space of VLIW Architectures
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MICRO
2007
IEEE
115views Hardware» more  MICRO 2007»
15 years 4 months ago
Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0
A significant part of future microprocessor real estate will be dedicated to L2 or L3 caches. These on-chip caches will heavily impact processor performance, power dissipation, a...
Naveen Muralimanohar, Rajeev Balasubramonian, Norm...
VLSID
2005
IEEE
102views VLSI» more  VLSID 2005»
15 years 10 months ago
Integrated On-Chip Storage Evaluation in ASIP Synthesis
An Application Specific Instruction Set Processor (ASIP) exploits special characteristics of the given application(s) to meet the desired performance, cost and power requirements....
Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar
DAC
2008
ACM
15 years 11 months ago
Specify-explore-refine (SER): from specification to implementation
Driven by increasing complexity and reliability demands, the Japanese Aerospace Exploration Agency (JAXA) in 2004 commissioned development of ELEGANT, a complete SpecC-based envir...
Andreas Gerstlauer, Junyu Peng, Dongwan Shin, Dani...
UIST
1997
ACM
15 years 2 months ago
The MetaDESK: Models and Prototypes for Tangible User Interfaces
The metaDESK is a user interface platform demonstrating new interaction techniques we call “tangible user interfaces.” We explore the physical instantiation of interface eleme...
Brygg Ullmer, Hiroshi Ishii
FCCM
2004
IEEE
144views VLSI» more  FCCM 2004»
15 years 1 months ago
Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine
In this paper we present a novel use of an FPGA as a computing element for streaming based application. We investigate the virtualized execution of dynamic reconfigurable tasks. We...
Matthias Dyer, Marco Platzner, Lothar Thiele