29 search results - page 1 / 6 » Exploring SW Performance Using SoC Transaction-Level Modelin... |
78
Voted
DATE
2003
IEEE
15 years 2 months ago
2003
IEEE
This paper presents VISTA, a new methodology and tool dedicated to analyse system level performance by executing full-scale SW application code on a transaction-level model of the...
88
Voted
ASAP
2005
IEEE
15 years 3 months ago
2005
IEEE
As billion transistor System-on-chips (SoC) become commonplace and design complexity continues to increase, designers are faced with the daunting task of meeting escalating design...
DATE
2006
IEEE
15 years 3 months ago
2006
IEEE
The ever increasing complexity and heterogeneity of modern System-on-Chip (SoC) architectures make an early and systematic exploration of alternative solutions mandatory. Efficien...
DATE
2005
IEEE
15 years 3 months ago
2005
IEEE
This paper gives an overview of a transaction level modeling (TLM) design flow for straightforward embedded system design with SystemC. The goal is to systematically develop both...
89
Voted
DAC
2004
ACM
15 years 2 months ago
2004
ACM
System-on-Chip (SoC) designs are increasingly becoming more complex. Efficient on-chip communication architectures are critical for achieving desired performance in these systems....