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ARCS
2009
Springer
15 years 4 months ago
Improving Memory Subsystem Performance Using ViVA: Virtual Vector Architecture
The disparity between microprocessor clock frequencies and memory latency is a primary reason why many demanding applications run well below peak achievable performance. Software c...
Joseph Gebis, Leonid Oliker, John Shalf, Samuel Wi...
SP
2006
IEEE
148views Security Privacy» more  SP 2006»
15 years 3 months ago
SubVirt: Implementing malware with virtual machines
Attackers and defenders of computer systems both strive to gain complete control over the system. To maximize their control, both attackers and defenders have migrated to low-leve...
Samuel T. King, Peter M. Chen, Yi-Min Wang, Chad V...
83
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LCTRTS
2004
Springer
15 years 2 months ago
Spinach: a liberty-based simulator for programmable network interface architectures
This paper presents Spinach, a new simulator toolset specifically designed to target programmable network interface architectures. Spinach models both system components that are ...
Paul Willmann, Michael Brogioli, Vijay S. Pai
ISCA
1996
IEEE
99views Hardware» more  ISCA 1996»
15 years 1 months ago
Coherent Network Interfaces for Fine-Grain Communication
Historically, processor accesses to memory-mapped device registers have been marked uncachable to insure their visibility to the device. The ubiquity of snooping cache coherence, ...
Shubhendu S. Mukherjee, Babak Falsafi, Mark D. Hil...
HPCA
2008
IEEE
15 years 9 months ago
Automated microprocessor stressmark generation
Estimating the maximum power and thermal characteristics of a processor is essential for designing its power delivery system, packaging, cooling, and power/thermal management sche...
Ajay M. Joshi, Lieven Eeckhout, Lizy Kurian John, ...