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ISSS
1995
IEEE
121views Hardware» more  ISSS 1995»
15 years 7 months ago
A comprehensive estimation technique for high-level synthesis
We present an integrated approach aimed at predicting layout area needed to implement a behavioral description for a given performance goal. Our approach is novel because: (1) it ...
Seong Yong Ohm, Fadi J. Kurdahi, Nikil Dutt, Min X...
DAC
2010
ACM
15 years 4 months ago
Automatic multithreaded pipeline synthesis from transactional datapath specifications
We present a technique to automatically synthesize a multithreaded in-order pipeline from a high-level unpipelined datapath specification. This work extends the previously propose...
Eriko Nurvitadhi, James C. Hoe, Shih-Lien Lu, Timo...
ANOR
2010
102views more  ANOR 2010»
15 years 4 months ago
Ejection chain and filter-and-fan methods in combinatorial optimization
The design of effective neighborhood structures is fundamentally important for creating better local search and metaheuristic algorithms for combinatorial optimization. Significant...
César Rego, Fred Glover
VLSID
2009
IEEE
155views VLSI» more  VLSID 2009»
16 years 4 months ago
Unified Challenges in Nano-CMOS High-Level Synthesis
: The challenges in nano-CMOS circuit design include the following: variability, leakage, power, thermals, reliability, and yield. This talk will focus on interdependent considerat...
Saraju P. Mohanty
DSN
2002
IEEE
15 years 9 months ago
32-Bit Cyclic Redundancy Codes for Internet Applications
Standardized 32-bit Cyclic Redundancy Codes provide fewer bits of guaranteed error detection than they could, achieving a Hamming Distance (HD) of only 4 for maximum-length Ethern...
Philip Koopman