Sciweavers

1136 search results - page 97 / 228
» Exploring the multiple-GPU design space
Sort
View
MICRO
2007
IEEE
115views Hardware» more  MICRO 2007»
15 years 10 months ago
Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0
A significant part of future microprocessor real estate will be dedicated to L2 or L3 caches. These on-chip caches will heavily impact processor performance, power dissipation, a...
Naveen Muralimanohar, Rajeev Balasubramonian, Norm...
VLSID
2004
IEEE
119views VLSI» more  VLSID 2004»
16 years 4 months ago
Rapid Prototyping for Configurable System-on-a-Chip Platforms: A Simulation Based Approach
The design of any application on a configurable System-on-a-Chip (SoC) like Atmel's FPSLIC is subject to a lot of constraints stemming from requirements of the application an...
Jens Bieger, Sorin A. Huss, Michael Jung, Stephan ...
FPL
2007
Springer
137views Hardware» more  FPL 2007»
15 years 10 months ago
Multi-processor System-level Synthesis for Multiple Applications on Platform FPGA
Multiprocessor systems-on-chip (MPSoC) are being developed in increasing numbers to support the high number of applications running on modern embedded systems. Designing and progr...
Akash Kumar, Shakith Fernando, Yajun Ha, Bart Mesm...
152
Voted
PPSN
2004
Springer
15 years 9 months ago
A Primer on the Evolution of Equivalence Classes of Bayesian-Network Structures
Bayesian networks (BN) constitute a useful tool to model the joint distribution of a set of random variables of interest. To deal with the problem of learning sensible BN models fr...
Jorge Muruzábal, Carlos Cotta
INFOCOM
2000
IEEE
15 years 8 months ago
Heuristics for Internet Map Discovery
— Mercator is a program that uses hop-limited probes—the same primitive used in traceroute—to infer an Internet map. It uses informed random address probing to carefully expl...
Ramesh Govindan, Hongsuda Tangmunarunkit